Wireless family
presentation
The Wireless family allows you to build your own software radio transmission channel on FPGAs, from the digital front-end (filtering, resampling, quantification) to the channel coding/decoding blocks
Based on your own system's constraints (sampling rate, useful signal bandwidth, adjacent channel rejection levels, etc.), you'll be able to determine the optimal filtering and resampling solution (by cascading elements like CIC, FIR, half-band filter, etc.), while optimizing quantification each step of the way.
Channel encoding and decoding components (5G-NR, LDPC, and Polar Coding) are available in VHDL format for various FPGA suppliers.
b<>com [DFE Rate Adaptor]
The design of receivers of digital signal is a key step in the development of communication systems, since it must ensure a good quality of the received signal, and at the same time a low complexity of the receiver. b<>com [DFE Rate Adaptor] has been created to help designing digital front ends by offering a generator of the components of the DFE (filters, rate adaptation, etc.) and a performance analysis of the latter.
A free test site is available here.
Do not hesitate to contact our experts via the form at the bottom of the page.
b<>com [Software Radio IoT]
Since 2020, there are more than 20 billion connected things in the world since 2020. While market expectations are huge, a handful of different technologies compete to provide connectivity to IoT nodes, thus leading to potential issues with interoperability, cost, performance and deployment. To tackle those issues, b<>com [Software Radio IoT] was conceived to accommodate several proprietary and 3GPP-based access technologies, and to offer outstanding reception performance thanks to cutting-edge digital filtering and patented demodulation algorithms.
