b<>com [Channel Processor] enables seamless wireless transmissions. It comes from the b<>com *Wireless Library* and implements Forward Error Correction (FEC) and Link Adaptation across a wide range of Physical Layers and standard specifications.
The [Channel Processor] is a parallel and efficient all-in-one IP architecture for both transmitter and receiver sides. Its generic FEC core supports many common standards such as Wi-Fi, LTE or 5G-NR by setting some specific parameters and configuring the mutualized architecture on the fly.
Features & benefits
Covers a large selection of systems and standards thanks to its specific upgradeable architecture.
Uses handshake-supporting customization to the Avalon and AXI bus interfaces. The flexible design allows easy dynamic adaptation.
Can be used on multiple targets (including major FPGA vendors).
Is capable of switching from one standard to another in a few clock cycles allowing low reconfiguration latency.
A test site for viewing the product's performance is available, click here.
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